# (C) 2001-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other 
# software and tools, and its AMPP partner logic functions, and any output 
# files any of the foregoing (including device programming or simulation 
# files), and any associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License Subscription 
# Agreement, Altera MegaCore Function License Agreement, or other applicable 
# license agreement, including, without limitation, that your use is for the 
# sole purpose of programming logic devices manufactured by Altera and sold by 
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# agreement for further details.


# TCL File Generated by Component Editor 10.1
# Tue Aug 17 16:32:25 MYT 2010
# DO NOT MODIFY


# +-----------------------------------
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from QSYS 12.0
# | 
package require -exact qsys 12.0
# | 
# +-----------------------------------

# +-----------------------------------
# | module fpoint
# | 
set_module_property NAME altera_nios_custom_instr_floating_point_2_combi
set_module_property VERSION 15.0
set_module_property INTERNAL false
set_module_property GROUP "DSP/Floating Point"
set_module_property AUTHOR "Altera Corporation"
set_module_property DISPLAY_NAME "Floating Point Hardware 2 Combinatorial"
set_module_property HIDE_FROM_SOPC true
set_module_property HIDE_FROM_QSYS true
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
set_module_property ANALYZE_HDL FALSE
# | 
# +-----------------------------------

# +-----------------------------------
# | file sets
# | 
set vhdl_filelist [list fpoint2_combi.vhd \
                   FPMinMaxFused/FPMinMaxFused.vhd \
                   FPCompareFused/FPCompareFused.vhd \
                   FPNeg_Abs/FPNeg.vhd \
                   FPNeg_Abs/FPAbs.vhd ]

add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL fpoint2_combi
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
foreach i $vhdl_filelist { add_fileset_file $i VHDL PATH $i }

add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL fpoint2_combi
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
foreach i $vhdl_filelist { add_fileset_file $i VHDL PATH $i }

add_fileset SIM_VHDL SIM_VHDL "" ""
set_fileset_property SIM_VHDL TOP_LEVEL fpoint2_combi
set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
foreach i $vhdl_filelist { add_fileset_file $i VHDL PATH $i }

# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1
# | 
add_interface s1 nios_custom_instruction end
set_interface_property s1 clockCycle 0
set_interface_property s1 operands 2
set_interface_property s1 opcodeExtensionLocked true
set_interface_property s1 opcodeExtensionLockedValue 224

set_interface_property s1 ENABLED true

add_interface_port s1 dataa dataa Input 32
add_interface_port s1 datab datab Input 32
add_interface_port s1 n n Input 4
add_interface_port s1 result result Output 32
# | 
# +-----------------------------------

# +-----------------------------------
# | set embeddedsw.configuration
# | 
# | 
# +-----------------------------------
